Dec 17
Toshiba Licenses Rambus XDR Memory Architecture for HDTV Chipset
Next-generation HDTVs to use 4.8Gbps XDR DRAM
LOS ALTOS, Calif — Dec 17, `07 –BUSINESS WIRE– Rambus today announced that Toshiba Corporation has licensed its XDR memory controller interface cell (XIO) and XDR memory controller (XMC) for next-generation high-definition television (HDTV) chipsets. The XIO and XMC will be implemented in Toshiba’s 65nm process. Operating at 4.8Gbps, the XDR memory architecture will allow Toshiba’s HDTV chipset to deliver state-of-the-art image processing performance in its customers’ HDTVs.
The XDR memory architecture uses patented Rambus innovations such as Octal Data Rate (ODR) technology, Differential Rambus Signaling Level (DRSL), and FlexPhase circuits to deliver the highest bandwidth available while using fewer DRAM devices than industry-standard memory solutions. Higher memory performance as delivered by the XDR architecture enables the advanced features of next-generation HDTVs such as 1080p+ resolution, 120Hz refresh rates, 12-bit color, multiple full HD Picture-in-Picture (PiP) data streams, and advanced image enhancement algorithms.More here.