East Fishkill, NY and TOKYO, Japan –December 18, `07 — IBM and Toshiba today announced that they have entered into a joint development agreement on 32nm bulk complementary metal oxide semiconductor (CMOS) process technology.
Since December 2005, IBM and Toshiba have collaborated on fundamental advanced research related to semiconductor process technologies at the 32nm technology generation and beyond at the research facilities in Yorktown and Albany, New York. Building on the success of this ongoing research collaboration, the two companies have agreed to extend the scope of the joint development work to now include 32nm bulk CMOS process technology.
Under the new agreement, Toshiba joins a six company IBM Alliance for 32nm bulk CMOS process technology development based in East Fishkill, New York.
Through this collaboration IBM and Toshiba plan to accelerate development of next-generation technology to achieve high-performance, energy-efficient chips at the 32nm process level, and to enhance the companies’ leadership in the global semiconductor industry.
“This agreement caps a year of extraordinary momentum for IBM and its semiconductor Alliance Partners,” said Gary Patton, vice president for IBM’s Semiconductor Research and Development Center. “In 2008 we’ll continue to strive to collectively deliver the industry breakthroughs and manufacturing milestones that come from talented engineers and semiconductor experts working in an open, collaborative environment with access to world class R&D facilities such as UAlbany NanoCollege’s Albany NanoTech complex.” More at Toshiba.
TOKYO, Japan — Dec 13, ‘07 — Toshiba today announced that it has achieved breakthroughs in three major basic technologies for 32nm generation system LSIs and beyond.
The advances are a major advance in metal gate electrode; a new structure and process technology for low resistance contacts that reduce contact resistance; and a technology for improving performance by changing the surface orientation of the silicon substrate. The new breakthrough will pave the way to 32nm LSIs and improve process efficiencies.
The three technologies were introduced at the IEDM (International Electron Devices Meeting) conference held at Washington DC, as major candidates for basic technologies for use in 32nm generation system LSIs and beyond. Toshiba will continue their development and optimization and aim for mass production in the first half of FY2010.
In developing the improved, new metal gate, Toshiba has realized a simplified manufacturing process technology that employs nickel silicide, a common material for both nMOS and pMOS transistors in a ratio of 1:3, respectively, and introduces an aluminum layer only in the nMOS gate.
For the low resistance contact, Toshiba employed a metal material in the source/ drain region, reducing contact resistance to a quarter in the nMOS side. The base electrode material is the same for both the nMOS and pMOS in pairs, and low-Schottky-barrier metal suitable for each type MOS transistor is segregated at interface of base material. The manufacturing process is simplified.
System LSI integrates CMOS elements, nMOS transistors and pMOS transistors. Therefore an optimized process is required. These new two technologies enhance performance and also contribute to an efficient manufacturing process. More at Toshiba.
Tokyo, Japan — Nov 27, ‘07 — Japanese chip makers Toshiba and NEC said on Tuesday they would jointly develop 32-nanometer chips to better keep up with rivals, reports Reuters.
“The companies will decide in 2008 how and if they will jointly produce the chips, they said.
Chip makers are racing to move to tinier circuit sizes to cut production cost per chip function and enable powerful electronics that run for hours without killing the battery. But the shift also forces changes in fundamental materials and processes and exposes chip makers to huge initial costs.
Samsung, IBM, Chartered Semiconductor, Infineon Technologies, STMicroelectronics and Freescale Semiconductor have said they would work through 2010 to develop and produce 32-nanometer chips. A nanometer is a billionth of a meter.
Toshiba and NEC Electronics, which plan to mass produce 45-nanometer or 40-nanometer chips by early 2009, had also approached Fujitsu, declined to comment on whether or not Fujitsu would join the group, only saying that Fujitsu was considering various options.” More at Reuters.
